Wire Crossing¶

File: pics/wire_crossing_yaml.pic.yml
Error caught: 1 short_error + 1 net_error + 6 open_errors — two routes on different nets cross on the metal layer. The crossing merges them into a single layout net that doesn't match the schematic.

import tempfile
from pathlib import Path

import elvis
import gdsfactory as gf
from IPython.display import Markdown
from kwasm import Tool, show

gf.gpdk.PDK.activate()

PICS = Path("../pics")
BUILD_GDS = Path("../build/gds")
BUILD_GDS.mkdir(parents=True, exist_ok=True)
PIC = PICS / "wire_crossing_yaml.pic.yml"

Schematic¶

A pad array (pad_array_inst) connects to a rectangle (mpd) via two independent routes. Each route forms its own net:

• route1: pad_array_inst,e13 → mpd,e3
• route2: pad_array_inst,e15 → mpd,e1

The rectangle has four ports (e1–e4) but only e1 and e3 are used.

schematic = elvis.load_schematics(PIC)
schematic

{'wire_crossing_yaml': {'instances': {'mpd': {'component': 'rectangle',
    'settings': {'layer': 'M3', 'size': [100, 20]}},
   'pad_array_inst': {'component': 'pad_array',
    'settings': {'port_orientation': 90}}},
  'routes': {'route1': {'links': {'pad_array_inst,e13': 'mpd,e3'},
    'routing_strategy': 'route_bundle_electrical',
    'settings': {}},
   'route2': {'links': {'pad_array_inst,e15': 'mpd,e1'},
    'routing_strategy': 'route_bundle_electrical',
    'settings': {'end_straight_length': 100, 'start_straight_length': 100}}},
  'ports': {},
  'placements': {'mpd': {'x': -500, 'y': 500, 'rotation': 90}},
  'name': 'wire_crossing_yaml'}}

Build from schematic¶

gds_path = BUILD_GDS / "wire_crossing_yaml.gds"
c = gf.read.from_yaml(schematic["wire_crossing_yaml"])
c.write_gds(gds_path)
show(gds_path, netlist=PIC, tools=[Tool.RULER, Tool.CLEAR_ALL, Tool.TOP_PORTS])

LVS Results¶

rdb = elvis.lvs_rdb(
    gds_path,
    schematic,
    short_layers=[(49, 0)],
    equivalent_ports={"pad": ["pad", "e1", "e2", "e3", "e4"]},
)
lyrdb = Path(tempfile.gettempdir()) / "wire_crossing.lyrdb"
rdb.save(str(lyrdb))
show(
    gds_path,
    lyrdb=lyrdb,
    netlist=PIC,
    tools=[Tool.SELECT, Tool.RULER, Tool.CLEAR_ALL],
)

Errors in detail:

print(f"ok={rdb.num_items() == 0}, error_count={rdb.num_items()}")
Markdown(elvis.error_summary(rdb))

ok=False, error_count=8

What Elvis Detected¶

The two routes cross on the metal layer, creating a geometric overlap. Because the routes belong to different nets in the schematic (route1 and route2 connect different port pairs), Elvis flags the overlap as a short.

The short merges all four route endpoints into a single layout net — {mpd,e1; mpd,e3; pad_array_inst,e13; pad_array_inst,e15} — which doesn't exist in the schematic: hence the missing_in_schematic net error. The remaining 6 errors are open ports on mpd and pad_array_inst that have no connection in either schematic or layout.

Why it matters¶

A wire crossing is only safe when both routes belong to the same net. Here the two routes serve different port pairs on the rectangle, so the crossing creates a real short. Elvis combines polygon-overlap detection with schematic-net identity: it reports the geometric overlap and the resulting net mismatch. See notebook 14 for a variant where an additional instance and different placement cause even more shorts.