Optical Short¶
File: pics/mzi_arms.pic.yml
Error caught: short — the two waveguide arms of the MZI cross and overlap on layer (1,0), creating a geometric short between two independent signal paths.
Error type: LVS.short
Expected: ok=False, error_count=2 (1 short + 1 missing_in_schematic net group derived from the short)
import tempfile
from pathlib import Path
import elvis
import gdsfactory as gf
from IPython.display import Markdown
from kwasm import Tool, show
gf.gpdk.PDK.activate()
PICS = Path("../pics")
BUILD_GDS = Path("../build/gds")
BUILD_GDS.mkdir(parents=True, exist_ok=True)
PIC = PICS / "mzi_arms.pic.yml"
Schematic¶
Components:
- splitter — 1×2 MMI: one input o1, two outputs o2 (upper) and o3 (lower)
- combiner — 2×2 MMI: inputs o1/o2, outputs o3/o4
- bottom_arm — route_bundle from splitter,o3 → combiner,o1; steps dx=20, dy=−20
- top_arm — route_bundle from splitter,o2 → combiner,o2; steps dx=20, dy=−40
The top arm starts from the upper splitter output (o2) but steers 40 µm downward, while the
bottom arm steers only 20 µm downward. The two routes therefore cross and physically overlap
in the silicon waveguide layer — this is the layout short we will detect.
{'mzi_arms': {'instances': {'combiner': {'component': 'mmi2x2',
'settings': {}},
'splitter': {'component': 'mmi1x2', 'settings': {}}},
'routes': {'bottom_arm': {'links': {'splitter,o3': 'combiner,o1'},
'routing_strategy': 'route_bundle',
'settings': {'radius': 10.0, 'steps': [{'dx': 20, 'dy': -20}, {'dx': 1}]}},
'top_arm': {'links': {'splitter,o2': 'combiner,o2'},
'routing_strategy': 'route_bundle',
'settings': {'radius': 10.0,
'steps': [{'dx': 20, 'dy': -40}, {'dx': 1}]}}},
'ports': {'o1': 'splitter,o1', 'o2': 'combiner,o3', 'o3': 'combiner,o4'},
'placements': {'combiner': {'x': 70, 'y': 0}, 'splitter': {'x': 0, 'y': 0}}}}
Build from schematic¶
Attention
The top arm of the MZI is folding the wrong way causing waveguide overlap. If the waveguide layer is listed as a possible short layer, it will be flagged as a short. Of course a 'short' for optical waveguides does not really make too much sense, but it's discovered by the same tool as electrical shorts and we chose not to change the name for this check.
gds_path = BUILD_GDS / "mzi_arms.gds"
c = gf.read.from_yaml(schematic["mzi_arms"])
c.write_gds(gds_path)
show(
gds_path,
netlist=PIC,
tools=[Tool.RULER, Tool.CLEAR_ALL, Tool.TOP_PORTS, Tool.DANGLING_PORTS],
)
rdb = elvis.lvs_rdb(gds_path, schematic, short_layers=[(1, 0)])
lyrdb = Path(tempfile.gettempdir()) / "mzi_arms.lyrdb"
rdb.save(str(lyrdb))
show(
gds_path,
lyrdb=lyrdb,
netlist=PIC,
tools=[Tool.SELECT, Tool.RULER, Tool.CLEAR_ALL],
)
flags used
The above LVS function is called with the following flags
- short_layers=[(1, 0)]
this can also be pre-configured.
Errors in detail:
print(f"ok={rdb.num_items() == 0}, error_count={rdb.num_items()}")
Markdown(elvis.error_summary(rdb))
ok=False, error_count=2
| cell | error type | description |
|---|---|---|
| mzi_arms | LVS.net.missing_in_schematic | Net {splitter,o2; splitter,o3; combiner,o1; combiner,o2} in layout but not in schematic |
| mzi_arms | LVS.short | Geometric short between 'combiner,o2 -> splitter,o2' and 'combiner,o1 -> splitter,o3' (2 locations) |
Geometric Short Detection via short_layers keyword¶
Pass short_layers=[(layer, datatype)] to enable polygon-level short checking.
Elvis runs a four-step pipeline:
- Chain building — instances are grouped into chains:
- Each connected sequence of 2-port route instances (straights, bends, tapers) forms one chain,
named after its reference-component endpoints, e.g.
"splitter,o3 -> combiner,o1". - Each multi-port reference component (splitter, combiner, pad, …) is its own single-instance chain.
- Bare polygons drawn directly in the top cell are collected into a single
top-cell polygonschain. - Polygon extraction — GDS boundaries on the specified layer are extracted per instance and
grouped by chain. Each chain's polygons are unioned into a single
MultiPolygon. - Overlap detection — all pairs of chains are tested for polygon intersection. Overlaps that fall exactly at port locations (where chains legitimately share a boundary) are filtered out.
- Schematic-aware suppression — a detected short is suppressed if all cross-chain port pairs it implies are already declared in the schematic (see the Fix section below for details).
Layer (1,0) is the silicon waveguide core in GDSFactory's generic PDK.
Note
The short (last error) is clearly shown as the overlap of the two routed waveguides. Through the (optical) short, all four arm-endpoint ports — splitter,o2, splitter,o3, combiner,o1, combiner,o2 — are physically tied to one electrical net in the layout, but the schematic declares them as two separate nets. Elvis collapses the four cross-pairs into one group LVS.net.missing_in_schematic error using set notation.
Fix¶
In this case this is easily fixed by making the top arm of the MZI point in the opposite direction. We leave this as an exercise to the reader.
Why it matters¶
Geometric shorts — where two independent signal paths physically overlap on the same layer — are invisible to connectivity-only LVS. They only become visible when polygon geometry is checked. Elvis's chain-based short detection finds these overlaps and maps them back to named schematic nets, giving actionable error messages rather than raw geometry coordinates.